Aswin G

I currently am a Silicon Design Engineer 2 at AMD, where I help in developing high-performance GEMM kernels for AMD Instinct GPUs. My current work focuses on pushing the boundaries of hardware efficiency by optimizing performance and resource utilization across various kernels, ensuring peak computational throughput for AI and HPC workloads.

With a career rooted in both hardware architectures and system software, I previously served as a Graphics Performance Engineer at Intel. There, I led initiatives in performance verification for GPU compute clusters (specifically thread dispatch and L1 cache), developing test content for measuring and validating peak performance for these RTL units, and creating automations and tools to improve PV efficiency.

I’ve done my B.E. in Computer Science from RNS Institute of Technology. I have a deep-seated interest in computer architecture and compilers as well. I’ve done a short research internship around RISC-V GCC compiler and also participated in the Winter Systems School conducted by IIT Delhi about Compilers and Distributed Computing. From assembly-level optimizations to architecting distributed systems, I am driven by the challenge of making hardware faster and software more efficient.

If you’re interested in any of things that I am (or just want to have a random conversation), feel free to reach out to me through any of the socials listed below for a chat!